1. Field of the Invention
The present invention generally relates to an input protection circuit which is applied to a semiconductor integrated circuit device having an SOI (silicon on insulator) structure, and more particularly, it relates to an SOI input protection circuit which is provided between an input pad and an internal circuit for protecting a MOSFET against breaking caused by a high voltage such as static electricity.
2. Description of the Background Art
FIG. 9 is a sectional view showing a conventional thin-film SOI-MOSFET. This thin-film SOI-MOSFET comprises a p.sup.- -type silicon substrate 1. A buried oxide film (BOX) 2 is formed on the silicon substrate 1. A silicon layer 20 is provided on the buried oxide film 2. A gate electrode 23 is provided on the silicon layer 20. A source region 21 and a drain region 22 are formed in the surface of the silicon layer 20, on both sides of the gate electrode 23.
FIG. 10 is a sectional view showing another conventional MOSFET having a bulk structure, which is precedent to the above thin-film SOI-MOSFET. Referring to FIG. 10, the conventional bulk-structure MOSFET comprises a p.sup.- -type silicon substrate 1. A gate electrode 23 is provided on the silicon substrate 1. A source region 21 and a drain region 22 are provided in the surface of the silicon substrate 1, on both sides of the gate electrode 23.
In the bulk-structure MOSFET shown in FIG. 10, a capacitor 24 is formed by contact surfaces of the source region 21 and the silicon substrate 1, while another capacitor 25 is formed by contact surfaces of the drain region 22 and the silicon substrate 1. In order to drive the bulk-structure MOSFET, therefore, it is necessary to first charge the capacitors 24 and 25, and hence a large quantity of power and a long time are required.
In order to solve this problem, the conventional thin-film SOI-MOSFET shown in FIG. 9 has been proposed. In the thin-film SOI-MOSFET, a capacitor 26 is formed between the source region 21 and the silicon substrate 1, while another capacitor 27 is formed between the drain region 22 and the silicon substrate 1. However, power is hardly necessary for charging these capacitors 26 and 27, since the same have small capacitances. Therefore, the thin-film SOI-MOSFET can be driven at a higher speed with lower power consumption as compared with the conventional bulk-structure SOI-MOSFET. In the thin-film SOI-MOSFET, further, radiation resistance is improved as compared with the conventional bulk-structure SOI-MOSFET, and high densification is possible. Due to these advantages, the thin-film SOI-MOSFET is watched with interest as a unit which can increase the speed of a semiconductor circuit device and implement a circuit device of an ultralow voltage and low power consumption which is applicable to a portable terminal or the like, and can be employed in a DRAM following that of 1 gigabit.
However, a problem which is specific to an SOI element has thereafter arisen also in such a semiconductor integrated device.
The present invention relates to solution of problems which are caused with respect to an input protection circuit, in particular.
FIG. 11 is a circuit diagram showing a conventional input protection circuit. A semiconductor integrated circuit device comprises an input pad and an internal circuit. Resistances 1 and 2 are provided between the input pad and the internal circuit. A protective transistor is provided between the resistances 1 and 2. The operation is as follows: When a nonstandardized voltage is applied to the input pad, the peak voltage is depressed by the resistance 1. Then, the current is pulled to a power source Vcc or GND by a punch through via the protective transistor. Further, the peak voltage is depressed by the resistance element 2, and the current is propagated to the internal circuit. Thus, the internal circuit elements can be prevented from breaking.
FIG. 12 is a plan view showing a protective transistor in an input protection circuit which is employed in a bulk structure. FIG. 13 is a sectional view taken along the line A--A in FIG. 12.
Referring to FIGS. 12 and 13, the protective transistor comprises a P-type silicon substrate 1. A LOCOS oxide film 7 is provided in the major surface of the P-type silicon substrate 1. An n.sup.+ diffusion layer 6 and another n.sup.+ diffusion layer 16 are provided to be isolated from each other by the LOCOS oxide film 7. The n.sup.+ diffusion layers 6 and 16 are a source and a drain of the protective transistor. An interlayer insulating film 5 is provided on the silicon substrate 1. The interlayer insulating film 5 is provided therein with contact holes 4a and 14a for exposing the surfaces of the n.sup.+ diffusion layers 6 and 16 respectively. The n.sup.+ diffusion layer 6 is provided with a first metal wire 4 having an end which is connected to an input pad, and another end which is connected to an internal circuit through a resistance 2. A second metal wire 14 is connected to the n.sup.+ diffusion layer 16. When a high voltage of 1000 to 10000 V by static electricity or the like is applied to the input pad, the input voltage is limited to about 3 V by a punch through across the source and the drain (across the n.sup.+ diffusion layers 6 and 16) of the protective transistor.
FIG. 14 is a plan view showing an input protection circuit which is formed by a diode by a P-N junction. FIG. 15 is a sectional view taken along the line A--A in FIG. 14.
Referring to FIGS. 14 and 15, the input protection circuit which is formed by only a diode by a P-N junction comprises a P-type silicon substrate 1. An n.sup.+ diffusion layer 6 is provided in the major surface of the silicon substrate 1. The n.sup.+ diffusion layer 6 is isolated from other element regions by a LOCOS oxide film 7 which is provided in the major surface of the silicon substrate 1. An interlayer insulating film 5 is provided on the silicon substrate 1. The interlayer insulating film 5 is provided therein with a contact hole 4a for partially exposing the surface of the n.sup.+ layer 6. The n.sup.+ layer 6 is connected with a metal wire 4 having an end which is connected to an input pad and another end which is connected to an internal circuit. When a high voltage by static electricity or the like is applied to the input pad, the input voltage is limited by an avalanche breakdown at the P-N junction of the drain (n.sup.+ diffusion layer 6).
In relation to such an input protection circuit, a problem which is specific to the aforementioned SOI element is now described.
FIG. 16 is a sectional view showing an SOI substrate. This SOI substrate consists of a silicon substrate 1, a buried oxide film 2, and a silicon layer 20. The buried oxide film 2 is formed by implanting oxygen into the silicon substrate 1. The silicon layer 20 and the buried oxide film 2 have thicknesses of 1000 .ANG. and 4000 .ANG. respectively.
In the input protection circuit, it is necessary to ensure a sufficient junction area, in order to avoid electric field concentration. When the aforementioned protection circuit is applied to an SOI substrate as such, however, no protection circuit can be structured. For example, the LOCOS oxide film 7, which is 6000 .ANG. in thickness, cannot be formed in the silicon layer 20. Due to the presence of the buried oxide film 2, further, no P-N junction can be formed along the thickness of the substrate.